The 55% Yield Line — Inside the Race to Mass-Produce 2-Nanometer Chips

Two billionths of a meter. That's the scale semiconductors — the brains inside everything from smartphones to AI data centers — have kept shrinking to squeeze out more performance. In late 2025, Taiwan's TSMC finally began mass-producing "2-nanometer" chips, with South Korea's Samsung and Japan's own Rapidus racing to catch up. Fought at a scale of a few dozen atoms, this contest is no mere bragging match: it quietly decides how long your phone's battery lasts and how much it costs to run an AI model.

A Gate Wrapped on All Four Sides — A Small Revolution

In the fourth quarter of 2025, TSMC began volume production of its next-generation N2 process on schedule. The biggest change is a new transistor shape. Instead of the "fin-shaped" FinFET design that has dominated chipmaking for years — where the gate grips the current-carrying channel from three sides — N2 introduces TSMC's first Gate-All-Around (GAA) structure, in which the gate wraps the channel on all four sides. That tighter grip cuts current leakage, making it possible to build transistors that are both smaller and more power-efficient.

According to press reports of TSMC's own figures, N2 delivers 10-15% faster performance at the same power draw as its previous N3E node, or a 25-30% cut in power use at the same speed, while packing in at least 15% more transistors. TSMC has scheduled volume production of N2P, an extension with further performance and power gains, for the second half of 2026.

The 55% Line — A Hard Climb for the Challengers

For Samsung, chasing from behind, no firm numbers have been published; what circulates is press reporting. On April 14, 2026, the Taiwanese research firm TrendForce relayed Korean media reports putting Samsung's 2-nanometer yield — the share of chips that come off the line defect-free — at around 55%, short of the roughly 60% generally considered necessary for stable mass production, and noted that major customer Qualcomm might choose TSMC instead. The same piece cites estimates of 60–70% for TSMC's 2-nanometer yield. None of these are figures disclosed by the companies themselves, and they vary by source.

Japan's Rapidus plans to begin 2-nanometer mass production in the second half of fiscal 2027 and to list its shares around fiscal 2031. In November 2025 the Ministry of Economy, Trade and Industry said it would invest ¥100 billion through the Information-technology Promotion Agency (IPA), and on February 27, 2026 the IPA announced that the investment had been made. According to press reports, the first orders Rapidus is pursuing are from companies that design custom chips for AI data centers. Whether a company with no mass-production experience can quickly raise yields that even the two leaders have struggled with can only be judged by results from fiscal 2027 onward.

Beyond 2 Nanometers — Building Up Instead of Out

So how much further can miniaturization go? One clue comes from an idea that looks less like shrinking and more like construction: stacking transistors like floors of a building instead of just packing them tighter on a flat plane. A preprint posted to the open-access repository arXiv in December 2025 (Athena et al., from a team spanning Stanford University, TSMC and ETH Zurich) describes a new way to build GAA nanosheet transistors directly on top of a chip's existing wiring layers, stacked in multiple tiers.

Until now, this kind of "add-on" transistor had a problem: the process used to lay down a thin, even insulating layer around the gate tended to damage the surrounding crystal structure, hurting performance. The team avoided this by reordering the steps — a method they call "channel-last" — and reported near-practical current performance, including an on-state current above 1 milliamp per micrometer. Rather than shrinking transistors further on a single flat layer, stacking them across multiple tiers — known as 3D integration — is increasingly seen as one of the leading paths beyond the 2-nanometer generation.

The contest over 2-nanometer chips isn't just about which country's company comes out on top. As the computing demands of training and running AI models keep climbing, how efficiently — and how close to home — a country can manufacture the chips underneath it all is increasingly framed as a question of economic security too. As of September 2026, what is firmly established goes only this far: TSMC is in volume production, and Rapidus is targeting the second half of fiscal 2027. For Samsung's yield, there are only press-reported figures.